
SV51008
2014.01.10
Table 7-3: DQ/DQS Bus Mode Pins for Stratix V Devices
Parity or
Data Pins per Group
DQ/DQS Groups in Stratix V E
7-5
QVLD
Mask
Mode
DQSn
Support
Data
(10)
CQn
Support (Optional) (Optional)
Typical
Maximum
Notes
x4
Yes
—
—
—
4
5
If you do not use differential DQS
and the group does not have
additional signals, the data mask
(DM) pin is supported.
x8/x9
Yes
Yes
Yes
Yes
8 or 9
11
Two x4 DQ/DQS groups are
stitched to create a x8/x9 group, so
there are a total of 12 pins in this
group.
x16/x18
Yes
Yes
Yes
Yes
16 or 18
23
Four x4 DQ/DQS groups are
stitched to create a x16/x18 group;
so there are a total of 24 pins in this
group.
x32/x36
Yes
Yes
Yes
Yes
32 or 36
47
Eight x4 DQ/DQS groups are
stitched to create a x32/x36 group,
so there are a total of 48 pins in this
group.
DQ/DQS Groups in Stratix V E
Table 7-4: Number of DQ/DQS Groups Per Side in Stratix V E Devices
Some of the x4 groups are using RZQ pins. If you use the Stratix V calibrated OCT feature, you cannot use these
groups.
Member Code
E9
EB
Package
1517-pin FineLine BGA
1932-pin FineLine BGA
1517-pin FineLine BGA
1932-pin FineLine BGA
Side
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
x4
58
58
70
70
58
58
70
70
x8/x9
29
29
35
35
29
29
35
35
x16/x18
14
14
16
16
14
14
16
16
x32/x36
6
6
6
6
6
6
6
6
(10)
The QVLD pin is not used in the UniPHY megafunction.
External Memory Interfaces in Stratix V Devices
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